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1 i n d e v e l o p m e n t figure 1. ut8r128k32 sram block diagram memory array 256k x 16 pre-charge circuit column select r o w s e l e c t a1 a2 a4 a5 a6 a7 a8 a9 data control i/o circuit data control a10 a11 a12 a13 a14 a15 dq(15) to dq(0) dq(31) to dq(16) e1 hhwe w e2 lhwe g a0 a16 low byte read circuit high byte read circuit a3 features q 15ns maximum access time q asynchronous operation, functionally compatible with industry-standard 128k x 32 srams q cmos compatible inputs and output levels, three-state bidirectional data bus - i/o voltage 3.3 volts, 1.8 volt core q radiation performance - total-dose: 100k rad(si) - sel immune >100 mev-cm 2 /mg - onset let > tbd - memory cell saturated cross section: tbd - neutron fluence: 3.0e14n/cm 2 - dose rate (estimated) - upset 1.0e9 rad(si)/sec - latchup >1.0e11 rad(si)/sec q packaging options: - 68-lead ceramic quad flatpack q standard microcircuit drawing 5962-03236 - qml compliant part introduction the ut8r128k32 is a high-performance cmos static ram organized as 131,072 words by 32 bits. easy memory expansion is provided by active low and high chip enables ( e1 , e2), an active low output enable ( g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to the device is accomplished by taking chip enable one ( e1 ) input low, chip enable two (e2) high and write enable ( w ) input low. data on the 32 i/o pins (dq0 through dq31) is then written into the location specified on the address pins (a0 through a16). reading from the device is accomplished by taking chip enable one ( e1 ) and output enable ( g ) low while forcing write enable ( w ) and chip enable two (e2) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the 32 input/output pins (dq0 through dq31) are placed in a high impedance state when the device is deselected ( e1 high or e2 low), the outputs are disabled ( g high), or during a write operation ( e1 low, e2 high and w low). standard products ut8r128k32 128k x 32 sram advanced data sheet may 29, 2003
2 i n d e v e l o p m e n t pin names device operation the ut8r128k32 has six control inputs called enable 1 ( e1 ), enable 2 (e2), write enable ( w ), half-word enables ( hhwe / lhwe ) and output enable ( g ); 17 address inputs, a(16:0); and 32 bidirectional data lines, dq(15:0). e1 and e2 device enables control device selection, active, and standby modes. asserting e1 and e2 enables the device, causes i dd to rise to its active value, and decodes the 17 address inputs to select one of 131,072 words in the memory. w controls read and write operations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. a(16:0) address w write enable dq(31:0) data input/output g output enable e1 enable (active low) v dd1 power (1.8v) e2 enable (active high) v dd2 power (3.3v) hhwe lwhe high half-word enable low half-word enable v ss ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 top view dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 v ss dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 v s s a 0 a 1 a 2 a 3 a 4 a 5 h h w e v s s l h w e w a 6 a 7 a 8 a 9 a 1 0 v d d 1 v d d 1 a 1 1 a 1 2 a 1 3 a 1 4 a 1 5 a 1 6 e 1 g e 2 v d d 2 v s s n c n c n c v d d 2 v s s dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 figure 2. 15ns sram pinout (68) 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 g w e2 e1 lhwe hhwe i/o mode mode x x x h x x dq(31:16) 3-state dq(15:0) 3-state standby x x l x x x dq(31:16) 3-state dq(15:0) 3-state standby l h h l l h dq(31:16) 3-state dq(15:0) data out low half-word read l h h l h l dq(31:16) data out dq(15:0) 3-state high half-word read l h h l l l dq(31:16) data out dq(15:0) data out word read x l h l l l dq(31:16) data in dq(15:0) data in word write x l h l l h dq(31:16) 3-state dq(15:0) data in low half-word write x l h l h l dq(31:16) data in dq(15:0) 3-state high half-word write h h h l x x dq(31:16) dq(15:0) all 3-state 3-state x x h l h h dq(31:16) dq(15:0) all 3-state 3-state
3 i n d e v e l o p m e n t read cycle a combination of w and e2 greater than v ih (min) and e1 less than v il (max) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 3a, is initiated by a change in address inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(31:0) after the specified t avqv is satisfied. outputs remain active throughout the entire cycle. as long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). sram read cycle 2, the chip enable-controlled access in figure 3b, is initiated by the latter of e1 and e2 going active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the 32-bit word addressed by a(16:0) is accessed and appears at the data outputs dq(31:0). sram read cycle 3, the output enable-controlled access in figure 3c, is initiated by g going active while e1 and e2 are asserted, w is deasserted, and the addresses are stable. read access time is t glqv unless t avqv or t etqv have not been satisfied. write cycle a combination of w and e1 less than v il (max) and e2 greater than v ih (min) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable-controlled access in figure 4a, is defined by a write terminated by w going high, with e1 and e2 still active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e1 or e2. unless the outputs have been previously placed in the high-impedance state by g , the user must wait user must wait t wlqz before applying data to the 32 bidirectional pins dq(15:0) to avoid bus contention. write cycle 2, the chip enable-controlled access in figure 4b, is defined by a write terminated by the latter of e1 or e2 going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by either e1 or e2 going active. for the w initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the sixteen bidirectional pins dq(31:0) to avoid bus contention. word enables separate byte enable controls ( lhwe and hhwe ) allow individual bytes to be accessed. lhwe controls the lower bits dq(15:0). hhwe controls the upper bits dq(31:16). writing to the device is performed by asserting e1 , e2 and the byte enables. reading the device is performed by asserting e1 , e2, g , and the byte enables while w is held inactive (high). radiation hardness the ut8r128k32 sram incorporates special design, layout, and process features which allows operation in a limited radiation environment. table 2. radiation hardness design specifications 1 notes: 1. the sram is immune to latchup to particles of 128mev-cm 2 /mg. 2. 10% worst case particle environment, geosynchronous orbit, 0.025 mils of aluminum. supply sequencing no supply voltage sequencing is required between v dd1 and v dd2 . hhwe lhwe operation 0 0 32-bit read or write cycle 0 1 16-bit high half-word read or write cycle (low byte bi-direction pins dq(15:0) are in 3 -state) 1 0 32-bit low half-word read or write cycle (high half word bi-direction pins dq(31:16) are in 3 -state) 1 1 high and low byte bi-directional pins remain in 3-state, write function disabled total dose 100k rad(si) heavy ion error rate 2 tbd errors/bit-day
i n d e v e l o p m e n t 4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd1 dc supply voltage -0.3 to 2.0v v dd2 dc supply voltage -0.3 to 3.8v v i/o voltage on any pin -0.3 to 3.8v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.2w t j maximum junction temperature +150 c q jc thermal resistance, junction-to-case 2 5 c/w i i dc input current 5 ma symbol parameter limits v dd1 positive supply voltage 1.7 to 1.9v v dd2 positive supply voltage 3.0 to 3.6v t c case temperature range (c) screening: -55 to +125 c (w) screening: -40 to +125 c v in dc input voltage 0v to v dd2
5 i n d e v e l o p m e n t dc electrical characteristics (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 1.0e5 rad(si). 1. measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. supplied as a design limit but not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. v ih = v dd2 (max), v il = 0v. symbol parameter condition min max unit v ih high-level input voltage .7* v dd2 v v il low-level input voltage .3* v dd2 v v ol low-level output voltage i ol = 8ma,v dd2 =v dd2 (min) .2* v dd2 v v oh high-level output voltage i oh = -4ma,v dd2 =v dd2 (min) .8* v dd2 v c in 1 input capacitance | = 1mhz @ 0v 7 pf c io 1 bidirectional i/o capacitance | = 1mhz @ 0v 7 pf i in input leakage current v in = v dd2 and v ss -2 2 m a i oz three-state output leakage current v o = v dd2 and v ss v dd2 = v dd2 (max), g = v dd2 (max) -2 2 m a i os 2, 3 short-circuit output current v dd2 = v dd2 (max), v o = v dd2 v dd2 = v dd2 (max), v o = v ss -100 +100 ma i dd1 (op 1 ) v dd1 supply current operating @ 1mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v , i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 15 ma i dd1 (op 2 ) v dd1 supply current operating @ 66mhz, inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 85 ma i dd2 (op 1 ) v dd2 supply current operating @ 1mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v , i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 1 ma i dd2 (op 2 ) v dd2 supply current operating @ 66mhz, inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 12 ma i dd1 (sb) 4 i dd2 (sb) 4 supply current standby @ 0hz cmos inputs , i out = 0 e1 = v dd2 -0.2, e2 = gnd v dd1 = v dd1 (max), v dd2 = v dd2 (max) 11 100 ma m a i dd1 (sb) 4 i dd2 (sb) 4 supply current standby a(16:0) @ 66mhz cmos inputs , i out = 0 e1 = v dd2 - 0.2, e2 = gnd, v dd1 = v dd1 (max), v dd2 = v dd2 (max) 11 100 ma m a
i n d e v e l o p m e n t 6 ac characteristics read cycle (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. guaranteed but not tested. 2. three-state is defined as a 200mv change from steady-state output voltage. 3. the et (enable true) notation refers to the latter falling edge of e1 or rising edge of e2. 4. the ef (enable false) notation refers to the latter rising edge of e1 or falling edge of e2. symbol parameter 8r128k32-15 min max unit t avav 1 read cycle time 15 ns t avqv address to data valid 15 ns t axqx 2 output hold time from address change 3 ns t glqx 2,1 g -controlled output enable time 0 ns t glqv g -controlled output data valid 7 ns t ghqz 2 g -controlled output three-state time 7 ns t etqx 2,3 e-controlled output enable time 5 ns t etqv 3 e-controlled access time 15 ns t efqz 4 e-controlled output three-state time 2 7 ns t blqx 1 lhwe , hhwe enable to output in low-z 0 ns t bhqz lhwe , hhwe enable to output in high-z 7 ns t blqv lhwe , hhwe enable to data valid 10 ns
7 i n d e v e l o p m e n t assumptions: 1. e1 and g < v il (max) and e2 and w > v ih (min) a(16:0) dq(31:0) figure 3a. sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g , hhwe , lhwe < v il (max) and w > v ih (min) a(16:0) figure 3b. sram read cycle 2: chip enable access latter of e1 low and e2 high data valid t efqz t etqv t etqx dq(31:0) figure 3c. sram read cycle 3: output enable access a(16:0) dq(31:0) g t ghqz assumptions: 1. e1 < v il (max) , e2 and w > v ih (min) t glqv t glqx t avqv data valid lhwe / hhwe t blqx t bhqz t blqv
i n d e v e l o p m e n t 8 ac characteristics write cycle (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. tested with g high. 2. three-state is defined as 200mv change from steady-state output voltage. symbol parameter 8r128k32-15 min max unit t avav 1 write cycle time 15 ns t etwh device enable to end of write 12 ns t avet address setup time for write ( e1 /e2- controlled) 0 ns t avwl address setup time for write ( w - controlled) 1 ns t wlwh write pulse width 12 ns t whax address hold time for write ( w - controlled) 2 ns t efax address hold time for device enable ( e1 /e2- controlled) 0 ns t wlqz 2 w - controlled three-state time 5 ns t whqx 2 w - controlled output enable time 4 ns t etef device enable pulse width ( e1/ e2 - controlled) 12 ns t dvwh data setup time 7 ns t whdx data hold time 2 ns t wlef device enable controlled write pulse width 12 ns t dvef data setup time 7 ns t efdx data hold time 0 ns t avwh address valid to end of write 12 ns t whwl write disable time 3 ns t blwh lhwe , hhwe low to write high 12 ns t blef lhwe , hhwe low to enable high 12 ns
9 i n d e v e l o p m e n t assumptions: 1. g < v il (max). (if g > v ih (min) then q(31:0) will be in three-state for the entire cycle.) w t avwl figure 4a. sram write cycle 1: w - controlled access a(16:0) q(31:0) e1 t avav d(31:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t avwh t whwl e2 lhwe / hhwe t blwh
i n d e v e l o p m e n t 10 t efdx assumptions & notes: 1. g < v il (max). (if g > v ih (min) then q(31:0) will be in three-state for the entire cycle.) 2. either e1 / e2 scenario can occur. a(16:0) figure 4b. sram write cycle 2: enable - controlled access w e1 d(31:0) applied data e1 q(31:0) t wlqz t etef t wlef t dvef t avav t avet t avet t blef t efax t efax or e2 e2 lhwe / hhwe
11 i n d e v e l o p m e n t data retention characteristics (pre and post-radiation) (v dd2 = v dd2 (min), 1 sec dr pulse) symbol parameter minimum maximum unit v dr v dd1 for data retention 1.0 v i ddr 1 data retention current 600 m a t efr 1,2 chip deselect to data retention time 0 ns t r 1,2 operation recovery time t avav ns v dd1 data retention mode t r 1.7v v dr > 1.0v figure 5. low v dd data retention waveform t efr e1 v dd2 v in <0.3v dd2 cmos e2 v ss v in >0.7v dd2 cmos 1.7v notes: 1. 50pf including scope probe and test socket. 2. measurement of data output occurs at the low to high or high to low transition mid-point (i.e., cmos input = v dd2 /2). 90% input pulses 10% < 2ns < 2ns cmos 0.0v v dd2 -0.05v figure 6. ac test loads and input waveforms 1.5v 188 ohms 50pf notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. e1 = v dd2 or e2 = v ss all other inputs = v dd2 or v ss 2. v dd2 = 0 volts to v dd2 (max) -55 c 125 c 25 c m a 12 ma 600
i n d e v e l o p m e n t 12 packaging notes: 1. all exposed metallized areas are gold plated over nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance with mil-prf-38535. figure 7. 68-lead ceramic quad flatpack
13 i n d e v e l o p m e n t ordering information 128k x 32 sram ut **** ** - * * * * * lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening: (c) = military temperature range flow (-55 c to +125 c) (p) = prototype flow (w) = extended industrial temperature range flow (-40 c to +125 c) package type: (w) = 68-lead ceramic quad flatpack access time: (15) = 15ns access time (68 cqfp) device type: (8r128k32) =128k x 32 sram notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per utmc manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
i n d e v e l o p m e n t 14 128k x 32 sram: smd 5962 - ******* ** lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (x) = 68-lead ceramic quad flatpack class designator: (q) = qml class q (v) = qml class v device type (01) = 15ns access time, cmos i/o, 68-lead ceramic quad flatpack (-55 c to +125 c) (02) = 15ns access time, cmos i/o, 68-lead ceramic quad flatpack (-40 c to +125 c) drawing number: 03236 total dose: (r) = 100k rad(si) federal stock class designator: no options * * * notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.

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